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[Com Port] UART

Description: UART_verilog,自己设计的异步串行收发。包括测试文件。-UART_verilog, designed to send and receive asynchronous serial. Including the test file.
Platform: | Size: 6144 | Author: 甲壳虫 | Hits:

[VHDL-FPGA-Verilog] S6_VGA_change

Description: verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
Platform: | Size: 2572288 | Author: 李晨 | Hits:

[VHDL-FPGA-Verilog] uartverlog

Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[VHDL-FPGA-Verilog] tx

Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send.
Platform: | Size: 7168 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] uartsourcecode

Description: uart的FPGA模块，基于VHDL、verilog语言-the FPGA UART modules, based on VHDL, verilog language
Platform: | Size: 293888 | Author: 王辉 | Hits:

[assembly language] lcd_module

Description: verilog code which receive from uart RX and then output to lcd text display.
Platform: | Size: 2048 | Author: 蔡俊仪 | Hits:

[VHDL-FPGA-Verilog] eeprom

Description: eeprom的Verilog HDL源代码，含eeprom的读写！Quartus II5.0平台测试通过！-EEPROM of the Verilog HDL source code, including reading and writing EEPROM! Quartus II5.0 platform test!
Platform: | Size: 521216 | Author: | Hits:

[Other Embeded program] UART

Description: 一个通用串口的verilog源程序，包含发送和接收模块-A universal serial Verilog source code, including sending and receiving modules
Platform: | Size: 53248 | Author: typhooncome | Hits:

[Com Port] rec

Description: uart串口通信程序 用VERILOG HDL　编写　可以有效应用于FPGA上-UART serial communication program with VERILOG HDL can be effectively used in the preparation of the FPGA
Platform: | Size: 1024 | Author: 德刚 | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] uart

Description:
Platform: | Size: 14336 | Author: 顾向南 | Hits:

[Com Port] uart_verilog

Description: UART接口被广泛应用在程序调适和信息输出。本实验将介绍UART接口的自测和调试实 例，通过这两个实例来掌握UART的设计方法和超级终端使用方法。-UART interface is widely used in the procedures and information to adjust the output. This experiment will introduce self-UART interface and debugging example, through these two examples to grasp the UART design methods and the use of HyperTerminal.
Platform: | Size: 36864 | Author: 沈天平 | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode_rtl.tar

Description: verilog实现的异步UART代码，包括发送模块、接收模块，波特率可配置，另附PC机的c代码-Verilog realize asynchronous UART code, including the transmission module, receiver module, the baud rate can be configured, an additional PC-c code
Platform: | Size: 38912 | Author: | Hits:

[VHDL-FPGA-Verilog] uart

Description: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Platform: | Size: 5120 | Author: 陈想 | Hits:

[VHDL-FPGA-Verilog] verilog_UART

Description: This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
Platform: | Size: 3072 | Author: keyoung | Hits:

[VHDL-FPGA-Verilog] uart_0

Description: 异步串行通信Uart接口设计，Verilog HDL程序，嵌入式必备哦-Asynchronous serial communication UART Interface Design, Verilog HDL procedures essential embedded Oh
Platform: | Size: 5120 | Author: 白雪 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[VHDL-FPGA-Verilog] UART_rec

Description: verilog 串口接收程序，在ACTEL Fusion FPGA上实验成功 和大家一起分享！^_^-Verilog serial receive process, ACTEL Fusion FPGA in the experimental success and share with everyone! ^ _ ^
Platform: | Size: 1024 | Author: whq | Hits:

[MPI] uart_dout

Description: 全双工UART口通信程序（Verilog版本）-Full-duplex UART port communication program (Verilog versions)
Platform: | Size: 439296 | Author: 张攀 | Hits:

[VHDL-FPGA-Verilog] USBUARTIICVGAcode

Description: verilog示例程序，很有实验和参考价值-verilog脢 戮 脌媒 鲁 脤脨貌 拢 卢 潞 脺脫脨脢渭脩茅 潞 脥 虏 脦 驴 录 录 脹脰渭
Platform: | Size: 503808 | Author: 猫 | Hits:
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